A Low-Radix and Low-Diameter 3D Interconnection Network Design
Dr. Jun Yang (杨峻)
Time: 14:00 on Dec. 26th, 2008 (Friday)
Location: Room 109, Meng Minwei Building Abstract: Interconnection plays an important role in performance and power of
CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has b
een proposed as a scalable and high-bandwidth fabric for interconnect design.
The advent of the 3D technology has provided further opportunity to reduce on-
chip communication delay. However, the design of the 3D NoC topologies has imp
ortant distinctions from 2D NoCs or off-chip interconnection networks. First,
current 3D stacking technology allows only vertical inter-layer links. Hence,
there cannot be direct connections between arbitrary nodes in different layers
− the vertical connection topology are essentially fixed. Second, the 3
D NoC is highly constrained by the complexity and power of routers and links.
Hence, low-radix routers are preferred over high-radix routers for lower power
and better heat dissipation. This implies long network latency due to high ho
p counts in network paths.
We design a low-diameter 3D network using low-radix routers. Our topology leve
rages long wires to connect remote intra-layer nodes. We take advantage of the
start-of-the-art one-hop vertical communication design and utilize lateral lo
ng wires to shorten network paths. Effectively, we implement a small-to-medium
sized clique network in different layers of a 3D chip. The resulting topology
generates a diameter of 3-hop only network, using routers of the same radix a
s 3D mesh routers. The proposed network shows up to 29% of network latency red
uction, up to 10% throughput improvement, and up to 24% energy reduction, when
compared to a 3D mesh network.
Dr. Jun Yang is an assistant professor of Electrical and Computer Engineering
at University of Pittsburgh, USA. She obtained her B.S. in CS from Nanjing Uni
versity in 1995, M.S. in Applied Math from Worcester Polytechnic Inst. in 199
7, and Ph.D. in CS from the University of Arizona in 2002. Prior to joining Pi
tt, she was an assistant professor in Computer Science and Engineering at Univ
ersity of California Riverside from 2002 to 2006. Her research interests are i
n microarchitecuture with emphases on low power microprocessor design, thermal
management, and 3D chip integration. She is a recipient of NSF CAREER award i
n 2008.
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